Papers

Last synced from Google Scholar: 2026-08-09

1. Evaluating Cross-Architecture Performance Modeling of Distributed ML Workloads Using StableHLO

   J Svedas, N Laubeuf, R Harvey, A Singh, C Man, A Nada, T Krishna, ...

   2026 IEEE International Symposium on Performance Analysis of Systems and …, 2026

2. A survey of end-to-end modeling for distributed DNN training: Workloads, simulators, and TCO

   J Svedas, H Watson, N Laubeuf, D Moolchandani, A Nada, A Singh, ...

   arXiv preprint arXiv:2506.09275, 2025

3. 27.2 M0N0: A performance-regulated 0.8-to-38MHz DVFS ARM cortex-M33 SIMD MCU with 10nW sleep power

   P Prabhat, B Labbe, G Knight, A Savanth, J Svedas, MJ Walker, S Jeloka, ...

   2020 IEEE International Solid-State Circuits Conference-(ISSCC), 422-424, 2020

Patents

1. SYSTEM, METHOD AND/DEVICE FOR MANAGING MEMORY DEVICES

   SSHU Gamage, FG Redondo, J Svedas

   US Patent US12314570B2, 2024

2. Checkpointing

   FG Redondo, SSHU Gamage, J Švedas, PAK Savanth

   US Patent US12327027B2, 2023

3. Signalling power level threshold event to processing circuitry

   SSHU Gamage, PAK Savanth, FG Redondo, J Švedas

   US Patent App. 18/309,364, 2023

4. Checkpoint-progress status

   FG Redondo, J Švedas, SSHU Gamage

   US Patent App. 18/316,614, 2023

5. Selective clock adjustment during read and/or write memory operations

   AW Chen, R Mathur, CN Dray, Y Sarrazin, JV Poitrat, Y Jallamion-Grive, ...

   US Patent US10896707B2, 2021

6. Cache sector usage prediction

   N Nikoleris, AL Sandberg, J Svedas, S Diestelhorst

   US Patent US10628318B2, 2020