CV
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R&D Project Leader
Full-time
- Modelling and evaluating distributed ML systems.
- Modelling and evaluating RISC-V based HPC architectures.
C++, Python
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Senior Research Engineer
Greater Cambridge Area
- Designed and verified M0N0, an ultra-low-power microcontroller chip with 10 uW active and 10 nW sleep power.
- Designed and verified a high-level MCU generator.
- Designed and verified Triffid, a batteryless and wireless energy harvesting chip.
- Designed and verified cryptographic hardware accelerators and Gen2 wireless codecs.
- Designed and implemented an intermittent computing firmware C library for Arm MCUs.
- Ran power simulations and RTL power optimisation.
- Designed PCB test circuits and performed chip testing.
- Developed resource-constrained embedded software for machine learning and IoT applications.
- Designed and maintained continuous integration and test regression infrastructure.
- Built a Keras/TensorFlow Lite pipeline for deploying a CIFAR-10 CNN with 6 kB RAM and 7 kB code.
- Worked with SLAM hardware/software pipelines and ROS.
Verilog, C, Python, embedded software, hardware verification
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Engineer, GPU
Greater Cambridge Area
- Performed functional UVM and formal Mali GPU hardware verification.
- Developed and maintained workflow automation tools and flows.
- Built hardware models in SystemVerilog and Python.
UVM, SystemVerilog, Verilog, Python
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Intern, ARM Media Processing Group
Greater Cambridge Area
- Designed and implemented a Python workflow automation tool to generate UVM verification components, RTL wrappers, and documentation.
Python
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Intern, ARM Media Processing Group
Greater Cambridge Area
- Implemented and integrated an AMBA based interconnect into a GPU subsystem.
Verilog
- linkedin.com/in/jonassvedas
- Scholar
- Google Scholar profile